ICs for Communications Quad ISDN 4B3T Echocanceller Digital Front End Quad IEC DFE-T PEB 24901 Version 1.2 PEF 24901 Version 1.2 Delta Sheet 06.96 T2490-112-L1-7600 PEB 24901 Revision History: Original version 06.96 Previous Releases: Page none Subjects (changes since last revision) Edition 06.96 This edition was realized using the software system FrameMaker. Published by Siemens AG, HL IT (c) Siemens AG . All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). 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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. Quad ISDN 4B3T Echocanceller Digital Front End (Quad IEC DFE-T) Delta Sheet PEB 24901 PEF 24901 CMOS This Delta Sheet refers to the PEB 24901 V1.1 as described in the "Preliminary Data Sheet 2.95" and the "Errata Sheet 01.96". The Quad IEC DFE-T V1.2 is an enhancement of the Quad IEC DFE-T V1.1. Being compatible to the V1.1, it provides the following new features: 1. IOM-Interface clock frequencies 2048 kHz and 8192 kHz added 2. Monitor message RST corrected 3. Boundary scan functions adapted 4. Power-on reset function enhanced 5. LT Repeater mode added 6. Delay in upstream direction changed in some operation modes 1 IOM-Interface Clock Frequencies The data clock frequency to be applied to pin DCL of the IOM interface may be 2048 kHz, 4096 kHz or 8096 kHz. Hence, either 4, 8 or 16 IOM-Channels are provided. The selection is done with two newly defined pins and the pin SLOT being renamed to SLOT0. Please refer to the Preliminary Data Sheet 2.95 of the PEB 24901 version 1.1 for a complete description of all pins. The following table lists new pins and pins with new functions only. SLOT2 is reserved for future use in order to cope with 32 IOM channels. Pin No. Symbol Input (I) Output (O) Description 55 SLOT 0 I IOM slot selection 0. Least significant bit. 45 SLOT1 I IOM-slot selection 1. Internal Pulldown. 32 SLOT 2 I IOM slot selection 2. Most significant bit. Reserved for future use. Connect to GND or leave open. Internal Pulldown. Semiconductor Group 4 06.96 PEB 24901 PEF 24901 The IOM Channel selection is: 2 SLOT2 SLOT1 SLOT0 Slots of ports 0..3 minimum DCL freq. (kHz) 0 0 0 0..3 2048 0 0 1 4..7 4096 0 1 0 8..11 8192 0 1 1 12..15 1 x x reserved for future use Monitor Message RST The second byte of the free running Monitor message "Report Status of STi1, STi0" is not corrupted to FFH anymore. 3 Boundary Scan * The pins TDI and TMS have an internal pullup resistor. * The content of the IDCODE-register of the boundary scan has been incremented to 0010. * The new pins SLOT2 and SLOT1 pins are included in the in the boundary scan. The table below gives the complete sequence: Boundary Scan Number TDI --> Pin Number Pin Name Type 1 63 TP1 I 1 2 62 TP2 I 1 3 61 CLS3 O 2 4 60 RESQ I 1 5 56 TSP I 1 6 55 SLOT0 I 1 7 53 LT I 1 8 52 CLS2 O 2 9 51 D3D I/O 3 10 50 D2D O 2 11 49 TP3 I 1 Semiconductor Group 5 Number of Scan Cells 06.96 PEB 24901 PEF 24901 Boundary Scan Number TDI --> Pin Number Pin Name Type 12 48 D1D I/O 3 13 47 D0D I/O 3 14 46 D3C I/O 3 15 45 SLOT1 I 1 16 44 D2C I/O 3 17 43 D1C I/O 3 18 42 D0C I/O 3 19 40 D3B I/O 3 20 39 D2B O 2 21 37 D1B O 2 22 35 D0B O 2 23 34 D3A O 2 24 33 D2A O 2 25 32 SLOT2 I 1 26 31 D1A O 2 27 30 D0A O 2 28 29 CLS0 O 2 29 28 ST00 I 1 30 27 ST01 I 1 31 26 ST10 I 1 32 24 ST11 I 1 33 23 ST20 I 1 34 21 ST21 I 1 35 20 CLS1 O 2 36 19 ST30 I 1 37 18 ST31 I/O 3 38 17 SDX O 2 39 15 DOUT O 2 40 14 DIN I 1 41 13 FSC I/O 3 Semiconductor Group 6 Number of Scan Cells 06.96 PEB 24901 PEF 24901 Boundary Scan Number TDI --> Pin Number Pin Name Type Number of Scan Cells 42 12 DCL I/O 3 43 11 PDM0 I 1 44 10 PDM1 I/O 3 45 8 PDM2 I 1 46 7 PDM3 I 1 47 5 SDR I/O 3 48 4 CL15 I 1 Note: I/O pins are bidirectional only for device test purpose. For the function of these pins refer to section 1.2 of the Preliminary Data Sheet 2.95. 4 Power-on Reset Proper operation of the internal power-on-reset is now provided, if the supply voltage has been below 1.0 V before applying power again. 5 LT Repeater Mode An LT-Repeater Mode programmable via Monitor command individually for all four ports is provided. The LT-RP Mode is enabled with the Monitor command 8150H. It is disabled with the Monitor command 8110H. The LT-RP Mode is disabled after power-on and reset. The state diagram of the LT-RP mode is given in fig. 1. Actication diagrams are depicted in the Preliminary Data Sheet 2.95 section 3.4.1, pages 34ff. 6 Delay in Upstream Direction In Upstream direction there is an additional delay of 125s (one IOM-frame) in LT Mode when a DCL frequency not equal to 4096 kHz is applied and in LT-RP Mode with all possible DCL frequencies. Semiconductor Group 7 06.96 PEB 24901 PEF 24901 (TE & U 0) Deac. Acknowledge U0, DIU (ARD | RSYD) { 0.5 ms } Deactivating U 0 , DA AR2 { 12 ms } DID Power Down U 0 , DIU DR AWR { 7 ms } ARD { 12 ms } Start Awaking U k0 U 2W, ARU (TE&/AR2) { 12 ms } AWT Awake Signal Sent U0, ARU (AR2&TE) DR DR DR (/AR2&AWR) { 7 ms } Ack. Sent/Received U 0 , ARU Sending Awake-Ack. U2W, ARU AWT { 7 ms } AWR DR TE NT-RP Synchronizing U2A, ARU DR ARD Synchronizing U4, ARU DR (U1| U3) Synchronizing U4, AIU { 12 ms } ARL DR DR (PFOFF&/ARL | LTD | RES | SSP) AID Data Transmission U 4 , AIU/RSYU Maintenance State U0/ SI, DA/HI DR TEST ANY STATE ITD09336 Figure 1 State Diagram of the LT Repeater Mode Semiconductor Group 8 06.96